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HANBit
HMD8M36M18G
32Mbyte(8Mx36) 72-pin FP with Parity MODE 2K Ref. SIMM Design 5V Part No. HMD8M36M18, HMD8M36M18G
GENERAL DESCRIPTION
The HMD8M36M18G is a 8M x 36bit dynamic RAM high density memory module. The module consists of sixteen CMOS 4M x 4bit DRAM in 24-pin SOJ packages and two CMOS 4Mx 4bit Quad-CAS DRAM in 28pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
PIN ASSIGNMENT FEATURES
w Part Identification HMD8M36M18---- 2048 Cycles/32ms Ref. Solder Lead HMD8M36M18G-- 2048 Cycles/32ms Ref. Gold Lead w Access times : 50, 60ns w High-density 32MByte design w Single + 5V 0.5V power supply w JEDEC standard PDpin and pinout w Fast Page with Parity mode operation w /CAS-before-/RAS refresh capability w/RAS-only and Hidden refresh capability w TTL compatible inputs and outputs w FR4-PCB design PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 -5 -6 M 14 15 16 17 18 SYMBOL Vss DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 Vcc NC A0 A1 A2 A3 A4 A5 A6 PIN 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SYMBOL A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 NC Vcc A8 A9 NC NC DQ26 DQ8 PIN 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 SYMBO L DQ17 DQ35 Vss /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 NC /WE NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 PIN 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL DQ12 DQ30 DQ13 DQ31 Vcc DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC Vss
OPTIONS
w Timing 50ns access 60ns access w Packages 72-pin SIMM
MARKING
PRESENCE DETECT PINS(Optional)
Pin PD1 PD2 PD3 PD4 50ns NC Vss Vss Vss 60ns NC Vss NC NC
SIMM TOP VIEW
PERFORMANCE RANGE
Speed 5 6 tRAC 50ns 60ns tCAC 13ns 15ns tRC 90ns 110ns
Note: A11 is used for only 4K Ref.
URL:www.hbeoc.kr REV.1.0 (August.2002)
-1-
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FUNCTIONAL BLOCK DIAGRAM
HMD8M36M18G
/CAS0 /RAS0
/CAS0 /RAS0 /OE /W
U2
A0-A10
DQ0 DQ1 DQ2 DQ3
DQ0-3
DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3
U11 /W
/CAS0 /RAS1 A0-A10 /OE
/CAS0 /RAS0 /OE /W
U4
A0-A10
DQ0 DQ1 DQ2 DQ3
U13 /W
DQ4-7
/CAS0 /RAS1 A0-A10 /OE
/CAS1
/CAS1 /RAS0 /OE /W
U6
A0-A10
DQ0 DQ1 DQ2 DQ3
U15 /W A0-A10
DQ9-12
/CAS1 /RAS1 /OE
/CAS1 /RAS0 /OE /W
U8
A0-A10
DQ0 DQ1 DQ2 DQ3
DQ0 DQ1 DQ13-16 DQ2 DQ3
U17 /W
/CAS1 /RAS1 A0-A10 /OE
/CAS0 /CAS1 /CAS2 /CAS3 /RAS0 /OE /W
U1
DQ0 DQ1 DQ2 DQ3
DQ8 DQ17 DQ26 DQ35
DQ0 DQ1 DQ2 DQ3 /W
U10
A0-A10
/CAS0 /CAS1 /CAS2 /CAS3 /RAS1 A0-A10 /OE
/CAS2
/CAS2 /RAS0 /OE DQ3 /CAS2 /RAS0 /OE DQ3
U3
/W
DQ0 DQ1 DQ2 A0-A10 DQ0 DQ1 DQ2 A0-A10 DQ0 DQ1 DQ2 A0-A10 DQ0 DQ1 DQ2 A0-A10
DQ0 DQ1 DQ18-21 DQ2 DQ3 DQ0 DQ1 DQ22-25 DQ2 DQ3 DQ0 DQ1 DQ27-30 DQ2 DQ3 DQ0 DQ1 DQ31-34 DQ2 DQ3
U12 /W
/CAS2 /RAS1 A0-A10 /OE
U5
/W
U14 /W
/CAS2 /RAS1 A0-A10 /OE
/CAS3
/CAS3 /RAS0 /OE DQ3 /CAS3 /RAS0 /OE DQ3
U7
/W
U16 /W
/CAS3 /RAS1 A0-A10 /OE
U9
/W
U18 /W
/CAS3 /RAS1 A0-A10 /OE Vcc Vss
0.1uF or Capacitor for each DRAM HANBit Electronics Co.,Ltd. 0.22uF
/WE A0-A10
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD8M36M18G
RATING -1V to 7.0V -1V to 7.0V 18W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP. 5.0 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL ICC1 -6 ICC2 ICC3 -6 -5 ICC4 -6 ICC5 ICC6 -6 Il(L) IO(L) VOH VOL ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=VIH, /RAS, Address cycling @tRC=min )
URL:www.hbeoc.kr REV.1.0 (August.2002)
SPEED -5
MIN -90 -10 2.4 -
MAX 1008 918 36 1008 918 828 738 18 1008 918 90 10 0.4
UNITS mA mA mA mA mA mA mA mA mA mA A A V V
Don't care -5
Don't care -5
-3-
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ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V VIN 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA )
HMD8M36M18G
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
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CAPACITANCE
( TA=25 C, Vcc = 5V, f = 1Mz ) DESCRIPTION SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1 MIN MAX 110 130 80 40 25 UNITS pF pF pF pF pF
Input Capacitance [A0-A11(A10)] Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
AC CHARACTERISTICS
( 0 C TA 70oC , Vcc = 5V10%, See notes 1,2.) -5 -6 UNIT MIN MAX MIN 110 50 13 25 3 3 2 30 50 13 50 13 20 15 5 0 10 10K 37 25 10K 13 50 3 3 2 40 60 15 60 15 20 15 5 0 10 10K 45 30 10K 13 50 60 15 30 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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o
STANDARD OPERATION Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time
URL:www.hbeoc.kr REV.1.0 (August.2002)
SYMBOL tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH 90
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Column address set-up time Column address hold time Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command hold referenced to /RAS Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge to /CAS hold time Access time from /CAS precharge /CAS precharge time (Fast page) /RAS pulse width (Fast page ) /W to /RAS precharge time (C-B-R refresh) /W to /RAS hold time (C-B-R refresh) tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCPA tCP tRASP tWRP tWRH 10 50 10 10 200K 0 5 10 5 30 0 10 25 0 0 0 10 50 10 13 13 0 10 64 0 5 0
HMD8M36M18G
ns ns ns ns ns ns ns ns ns ns ns ns ns 64 ns ns ns ns ns 35 10 60 10 10 200K ns ns ns ns ns
10 30 0 0 0 10 55 10 15 15 0 15
10 5
NOTES 1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC. 5.Assumes that tRCD tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
URL:www.hbeoc.kr REV.1.0 (August.2002)
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TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE
HMD8M36M18G
VIH/RAS
tRC tRAS tCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
tRP
VILtCSH tRSH tCAS tRAL tCRP
/CAS VIH-
VILVIHA
VILVIH-
ROW ADDRESS
tRCS
/W
tRRH tAA tCAC tCLZ
tRCH
VIL-
tOFF
DQ0-DQ7 VOHVOL-
tRAC
OPEN
DATA-OUT
TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE) NOTE : Dout = Open
tRC
/RAS VIH-
tRAS tCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
tRP
VILtCSH tRSH tCAS tRAL tCRP
VIH/CAS
VILVIHVILROW ADDRESS
A
tCWL tRWL tWCS tWCH tWP tDS tDH
DATA-IN
VIH/W VIL-
DQ0-DQ7
VOHVOL-
URL:www.hbeoc.kr REV.1.0 (August.2002)
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PACKAGING INFORMATION
SIMM Design (Front)
HMD8M36M18G
0.25 mm MAX
2.54 mm MIN
1.29 0.08mm
Gold : 1.040.10 mm 1.27 Solder:0.9140.10mm
ORDERING INFORMATION
Part Number
Density
Org.
Package
Vcc
SPEED
HMD8M36M18G-5 HMD8M36M18G-6
32MByte 32MByte
8MX 36bit 8MX 36bit
72 Pin-SIMM 72 Pin-SIMM
5.0V 5.0V
50ns 60ns
URL:www.hbeoc.kr REV.1.0 (August.2002)
-7-
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